Weebit Nano Launches Matrix ReRAM Research Program for In-Memory AI Computing

Weebit Nano has launched the Weebit Matrix In-Memory Compute Research Program, giving academic and industry researchers access to ReRAM hardware for testing a different way to run AI calculations: perform them where the data is stored. The program provides research kits built around a 32 × 32 crossbar array, with support for operations including vector-matrix multiplication, convolution, and spiking neural networks.

It targets an important hardware question for edge AI: how much energy and time can be saved by reducing repeated transfers between memory and a separate processor? This is a research-platform launch, rather than a finished commercial AI accelerator. Weebit says technical challenges remain before an in-memory computing solution reaches the commercial market. The immediate objective is to let researchers move from models and simulations to experiments on actual ReRAM hardware.

Neural-network inference repeatedly combines inputs with stored model weights. In a conventional architecture, moving those values through the memory hierarchy can consume bandwidth and energy. In-memory computing, or IMC, seeks to perform some of that work within the memory array itself. Resistive random-access memory, or ReRAM, stores information…